Information processing apparatus including a large number of CPUs (Central Processing Units) such as large-scale servers are increasing. In the apparatus including the many CPUs, communication between the CPUs occur in a data read to a certain CPU from a memory involved in another CPU and a data write from a certain CPU to a memory involved in another CPU, which becomes a factor of lowing performance. In order to remedy the performance deterioration, there has been proposed shared memory technology in which a plurality of CPUs uses the same memory as a main storage.
Methods to write data from a cache memory of a CPU to a memory being a main storage include a write-back method and a write-through method. The write-back method is capable of executing a memory access at a high speed though sometimes temporarily impairing consistency of data between the cache memory and the main storage. The write-through method is capable of constantly keeping consistency of data between the cache memory and the main storage, but on the other hand, has a difficulty in executing a memory access at a high speed.
There has been proposed an apparatus that controls whether to execute a data write from a cache memory to a memory being a main storage by the write-back method or the write-through method. For example, there has been proposed an apparatus that performs the control according to an access address so that a data write is executed by the write-back method for a certain area requiring a high-speed access and a data write is executed by the write-through method for a certain area requiring consistency of data (for example, refer to Patent Document 1). There has also been proposed an apparatus that controls whether to execute a data write by the write-back method or by the write-through method, according to tag information of a data block stored in a cache line, for instance (for example, refer to Patent Document 2).
[Patent Document 1] Japanese Laid-open Patent Publication No. 08-83215
[Patent Document 2] Japanese Laid-open Patent Publication No. 11-282750
In a shared memory environment, a plurality of CPUs are capable of using the same memory, and performance deterioration due to the occurrence of the communication between the CPUs may be suppressed. Writing data from a cache memory of a CPU to a memory being a main storage by the write-back method enables the execution of a memory access at a high speed.
However, in the shared memory environment, when data are written from the cache memory to the memory being the main storage by the write-back method, some data is held in the cache memory for a long period before being written back to the memory. Accordingly, when some CPU fails, if the write of the data to the common memory from the cache memory of this CPU is not completed, the plural CPUs are influenced and the whole information processing apparatus sometimes stops.